verilog, 198 bytes

Result

AC

Duration

526ms

Code [DL]

module m;integer X[0:11],v,s;initial begin
for(v=0;$fscanf(1<<31,"%d",X[v]);v+=1)X[v]-=v>2?X[v%3]:0;for(s=0;v>9;v-=1)s+=X[v-1]*(X[v%3+3]*X[(v+1)%3+6]-X[v%3+6]*X[(v+1)%3+3]);$write(s/6);end
endmodule

stdin

22 92 06
58 36 35
31 91 36
16 04 35

stdout

      15925

stderr

strace