verilog, 227 bytes

Result

WA

Duration

495ms

Code [DL]

module z;time a,b,c,d,e,f,g,h,i,j,k,l,z;initial begin z=$fscanf(1<<31,"%d%d%d%d%d%d%d%d%d%d%d%d",a,b,c,d,e,f,g,h,i,j,k,l);--d;e-=b;f-=c;g-=a;h-=b;i-=c;j-=a;k-=b;l-=c;$write((g*k*f+j*e*i+d*h*l-j*h*f-d*k*i-g*e*l)/6);end endmodule

stdin

63 27 04
29 72 05
40 76 93
60 70 43

stdout

 3074457345618254246

stderr

strace