verilog, 225 bytes

Result

WA

Duration

493ms

Code [DL]

module z;integer a,b,c,d,e,f,g,h,i,j,k,l,z;initial begin z=$sscanf("%d%d%d%d%d%d%d%d%d%d%d%d",a,b,c,d,e,f,g,h,i,j,k,l);d-=a;e-=b;f-=c;g-=a;h-=b;i-=c;j-=a;k-=b;l-=c;$write((g*k*f+j*e*i+d*h*l-j*h*f-d*k*i-g*e*l)/6);end endmodule

stdin

42 46 50
45 68 80
05 30 18
18 20 83

stdout

          x

stderr

strace