verilog, 45 bytes

Result

WA

Code [DL]

module c;real d;initial $write(2e3);endmodule

stdin

10001000
01000010
00000100
00011011
01011010
01000000
00000110
00011100
00110111
00100100
01001110
10001110
01100001
11110001
10101111
10000101
00000011
01101101
10000010
11010010
00010001
10010101
01100011
00000001
01101001
00000000
01001101
01011011
00010101
11100111
00101110
00101101
11000111
10011001
11000101
00001010
01111000
01000100
10100110
11100111
11111101
01111101
11101101
10010011
00001111
01111000
11110000
10111110
10101011
00110101

stdout

2000.00

stderr

strace