verilog, 65 bytes

Result

WA

Code [DL]

module _;real x;
always
$write("%d",1==(8*x+1)**0.5%2);
endmodule

stdin

00000110
10011001
10101101
11000100
00000011
11111101
01011011
01000001
10111110
11100111
10110111
01111000
01101001
10110001
00011100
00001010
11101011
00001010
00100110
00010101
11100101
00011010
01101110
10100100
11011101
00001110
10100110
10001000
01110101
11001100
00001111
00000000
01010011
00000001
10001011
10111011
01100011
10111000
10011111
11010010
01000010
10101011
10001000
00110111
01001110
01100000
00100100
00101101
01100101
10111100

stdout

stderr

/volume/CODE:2: error: always statement does not have any delay.
/volume/CODE:2:      : A runtime infinite loop will occur.
Elaboration failed
/home/esolang/bin/verilog: line 4: /tmp/code: No such file or directory
rm: cannot remove '/tmp/code': No such file or directory

strace