by@xuzijian629_key
WA
module a;initial repeat(50)$write("%d",$fscanf(1<<31,"%b",x));endmodule
01001110 00000011 00100111 11010111 01100011 10110001 11011001 01101001 11010110 00111111 00000000 10000111 00001111 01001111 00101011 11001110 00101101 00001001 10000110 00011100 11110101 11111101 01111000 10101100 10111000 01011011 10111111 11001101 01111000 10111110 10111011 00000110 00010101 11100111 00110111 10100101 01010100 11010010 10011001 10101011 00101100 00100100 10011001 00101000 00001010 01111111 10001000 11011100 00000001 01000010
/volume/CODE:1: error: Unable to bind wire/reg/memory `x' in `a' ivl: netmisc.cc:467: void eval_expr(NetExpr*&, int): Assertion `expr' failed. Aborted (core dumped) /home/esolang/bin/verilog: line 4: /tmp/code: No such file or directory rm: cannot remove '/tmp/code': No such file or directory