verilog, 79 bytes

Result

WA

Code [DL]

module c;reg d;initial while($fscanf(1<<31,"%b",d))$write($sqrt(d*8));endmodule

stdin

10001100
10010101
11100111
00000011
11111001
01001000
11111010
00010101
10101000
00001110
00001100
00001010
11111101
01010000
00100111
01101001
01011011
01011000
10001011
10001000
11111101
01001110
01001100
00011100
00001111
01111110
00100100
01111000
11010100
10101011
00000001
00110111
00000111
00000110
11010010
00001001
00000000
00101101
11101010
11111110
10011001
01000010
01000010
10010100
01010110
10100101
10111110
00010111
00110001
10110001

stdout

0.000002.828432.828432.828432.828430.000000.000002.828430.000000.000000.000000.000002.828430.000002.828432.828432.828430.000002.828430.000002.828430.000000.000000.000002.828430.000000.000000.000000.000002.828432.828432.828432.828430.000000.000002.828430.000002.828430.000000.000002.828430.000000.000000.000000.000002.828430.000002.828432.828432.82843

stderr

strace