by@satos___jp
WA
module a;
integer i,j,x,c;
initial begin
for (i=0;i<10;i=i+1) begin
c = $fscanf(32'h8000_0000,"%b",x);
for(j=0;j<x;j++) begin
if (j*(j+1)/2==i) begin
c = 0;
end
end
$write("%d\n",1-c);
end
end
endmodule
01000100 00000111 00001010 01010111 10100110 11100111 10100000 01001011 10001011 11001110 01101001 00000110 10101011 00010101 10111110 00011100 10000011 00000000 00000001 00110111 00000011 11111101 00000000 10111100 01110101 00101101 01111000 01011011 11110111 11100100 01110111 01101111 10011001 01010010 01111111 11010010 01000010 10101011 00100100 11110110 11100010 10001000 00011111 11110000 10101101 01100001 01001000 01001110 01011110 00001111
/volume/CODE:6: syntax error /volume/CODE:6: error: Error in for loop step assignment. /home/esolang/bin/verilog: line 4: /tmp/code: No such file or directory rm: cannot remove '/tmp/code': No such file or directory