by@satos___jp
WA
module a;
integer i,j,x,b;
initial begin
for (i=0;i<10;i=i+1) begin
c = $fscanf(32'h8000_0000,"%b",x);
$write("%d %d\n", x,c);
end
end
endmodule10011000 10010110 10101011 10011001 10001000 01101000 01101001 00100100 00110100 01011100 11010010 00110111 00011100 10111110 11101001 10010010 10000001 00001111 00000011 00110010 10011111 00101101 01001110 00000001 00000000 01000010 11000011 11100100 01111111 11100111 00001010 00000110 10011110 10111111 00001010 01111000 11011001 01100001 00001011 01011011 11101110 11111110 11011010 11111101 00100100 00010100 01110101 01001000 00010101 01011101
/volume/CODE:5: error: Could not find variable ``c'' in ``a'' /volume/CODE:6: error: Unable to bind wire/reg/memory `c' in `a' 2 error(s) during elaboration. /home/esolang/bin/verilog: line 4: /tmp/code: No such file or directory rm: cannot remove '/tmp/code': No such file or directory