verilog, 85 bytes

Result

WA

Code [DL]

module c;real d;initial while($fscanf(1<<31,"%b",d))$write(+$sqrt(d*8+1)%2);endmodule

stdin

01110110
11111101
11010010
11001111
00010000
10110101
10111110
00100100
01101001
01001110
10111010
00110111
01100101
00110010
01011011
10011001
01101101
10101111
00001111
10010011
00000001
00000001
00011100
00000110
01000010
00001101
00011000
01010110
00000000
01111000
10101011
10100010
01111101
00001010
01000010
11001011
00100110
00000011
10011000
11100111
00010101
10001000
10100000
00111000
00010001
00101101
10011101
11010000
10111100
01101100

stdout

0.7408521.000001.000000.7062651.357820.06573261.000001.000001.000001.000000.5875631.000000.4429250.02498441.000001.000001.546571.429931.000000.3074341.000001.000001.000001.000001.000000.2469511.892440.2488091.000001.000001.000000.01388621.638581.000001.000000.3112891.464251.000000.8855271.000001.000001.000001.791061.189621.704701.000001.454200.8044120.7943291.41088

stderr

strace