verilog, 51 bytes

Result

WA

Code [DL]

module c;real d;initial $write("%d",0>>1);endmodule

stdin

01110010
00001111
01100001
10100000
10100001
01110111
11010010
01100000
01000010
10111110
01101011
00101001
00101111
00010101
00011100
00001110
10011001
00101011
00100100
00110111
01101001
10011110
01110001
00000110
00111111
01110000
01101100
00100011
01010101
00001010
11100111
10101011
11111101
10001000
00000011
00010010
10010100
00111100
11100000
10101011
00000011
01110110
00101101
01111000
00000001
01110100
10011100
01001110
00000000
01011011

stdout

0

stderr

strace