verilog, 84 bytes

Result

WA

Code [DL]

module a;real x;initial while($fscanf(1<<31,"%b",x))$write((8*x+1)**0.5%1);endmodule

stdin

01101001
01000010
00000011
01011011
01111011
10100101
10101001
11101101
01011010
00001111
10111110
00101111
00110101
01110111
10110110
11101001
01111110
11010010
00000001
01011100
11101111
00110111
11010001
01001110
01000110
10101011
01001100
10000111
00101011
10001000
10001111
00011100
10100001
00001010
00011010
01010000
00101101
10011001
00000110
10111010
00010101
01011011
00100100
00000000
11001101
01001110
01111000
01110001
11111101
11100111

stdout

0.000000.000000.000000.000000.3847100.3455640.7831480.5545630.8514430.000000.000000.4164880.6155280.8706980.1706690.1856460.7647600.000000.000000.1477440.7378550.000000.9023230.000000.6854390.000000.6779250.8785640.5741760.000000.8378490.000000.9026460.000000.4568320.3179780.000000.000000.000000.5875630.000000.000000.000000.000000.5092580.000000.000000.08321790.000000.00000

stderr

strace