verilog, 86 bytes

Result

WA

Code [DL]

module a;integer x;initial while($fscanf(1<<31,"%b",x))$write((8*x+1)**0.5);endmodule

stdin

01100010
00000001
11111101
00000110
01110111
01111000
11100010
11101110
00101101
10011010
00001111
11100111
00000000
00100001
11010010
00110001
01011011
00010010
00011100
01111010
10101101
01001110
11011001
00001010
10000101
10111011
00101011
10000100
10001000
01010111
01000000
11001011
10101011
11110101
10111110
10100010
00011100
01101001
01000010
00010101
11010101
00100100
10011001
00101110
11101001
10010011
00110111
10001000
00000011
01010011

stdout

28.01793.0000045.00007.0000030.870731.000042.532343.646319.000035.114111.000043.00001.0000016.278841.000019.824227.000012.041615.000031.257037.215625.000041.67739.0000032.634338.691118.574232.511533.000026.400822.649540.311337.000044.283239.000036.013915.000029.000023.000013.000041.291617.000035.000019.209443.185634.307421.000033.00005.0000025.7876

stderr

strace