verilog, 83 bytes

Result

WA

Code [DL]

module a;real x;initial while($fscanf(1<<31,"%b",x))$write((8*x+1)**0.5);endmodule

stdin

00000000
11011001
10111110
01101100
00100100
00000001
10101000
11110101
01101001
10001100
11010010
01010010
11111101
10011001
10101111
01011011
00011100
11100111
11010111
01111000
11000101
00001010
10101011
11101111
01000010
10110010
10011100
11000100
11000111
10101011
00010101
01001110
10000011
10001000
00101101
00000110
11100000
11001100
00100101
11001111
01101111
00000010
10110000
00010110
11111100
00110111
00001111
11110010
00000011
00000001

stdout

1.0000041.677339.000029.410917.00003.0000036.674244.283229.000033.481341.000025.632045.000035.000037.429927.000015.000043.000041.484931.000039.71159.0000037.000043.737923.000037.749235.341239.610639.912437.000013.000025.000032.388333.000019.00007.0000042.343840.410417.233740.706329.81614.1231137.536613.304144.911021.000011.000044.01145.000003.00000

stderr

strace