verilog, 85 bytes

Result

WA

Code [DL]

module a;real x;initial while($fscanf(1<<31,"%b",x))$write((8*x+1)**0.5%2);endmodule

stdin

00111110
00000111
11110110
00010101
01111000
01001110
10111110
00010011
11100111
11111101
11010110
10011001
10001000
11011011
01110001
00001111
10100010
00100100
00101111
10101111
01110110
01111010
10001100
01010011
01011011
01000100
00010101
00000101
00010000
10011111
00000011
00110111
01010100
01010110
11010010
00101101
00101001
01010010
00110111
10101011
00011100
01000010
01101001
00001010
00000110
00000001
00000000
00110010
01000000
01011001

stdout

0.2934971.549830.3734151.000001.000001.000001.000000.3693171.000001.000001.388401.000001.000001.868840.08321791.000000.01388621.000001.416491.429930.7408521.257001.481341.787591.000001.345241.000000.4031241.357821.679131.000001.000001.942240.2488091.000001.000000.1383571.632011.000001.000001.000001.000001.000001.000001.000001.000001.000000.02498440.6495030.702060

stderr

strace