verilog, 84 bytes

Result

WA

Code [DL]

module c;real d;initial while($fscanf(1<<31,"%b",d))$write($sqrt(d*8+1)%2);endmodule

stdin

00000000
10101011
11110011
00011101
00111010
01100111
00101101
10010111
00001010
00000110
01010000
10111000
01000010
10110000
01101001
00000001
01001110
11011110
10011001
00100100
10101001
11100111
10101000
10101111
11011101
01001001
11100000
10000100
10111110
00001111
01010111
01001010
00011100
10001000
00000011
11111101
00010101
10001100
11000111
11111010
10011001
11001110
11010010
10001111
00110010
00110111
01111000
01111000
01011011
01000000

stdout

1.000001.000000.1021541.264341.563860.7228131.000000.7706771.000001.000001.317980.3796821.000001.536651.000001.000001.000000.1544781.000001.000000.7831481.000000.6742421.429930.05948170.1867730.3438310.5115361.000001.000000.4007580.3515911.000001.000001.000001.000001.000001.481341.912400.7325381.000000.6078811.000001.837850.02498441.000001.000001.000001.000000.649503

stderr

strace