verilog, 87 bytes

Result

WA

Code [DL]

module c;integer d;initial while($fscanf(1<<31,"%b",d))$write($sqrt(d*8+1)%2);endmodule

stdin

10110010
10000100
00110111
01001110
00000000
00110100
00000000
01010111
11011000
10111110
01010101
00101110
00011100
00000001
10010110
00001001
10001111
10001000
01110111
00001110
01111000
01001100
01011111
10011001
00111111
10101100
10101011
11100001
00010011
00101101
11000110
00000110
00010101
00000011
00001111
00001010
01000010
01011011
01000010
10010001
11010010
00100100
11010101
11100111
11001111
11110110
00111000
10010010
11111101
01101001

stdout

1.749170.5115361.000001.000001.000000.4205781.000000.4007581.581251.000000.09597671.209371.000001.000000.6554470.5440041.837851.000000.8706980.6301461.000000.6779251.586231.000000.4722051.107951.000000.4381900.3693171.000001.812061.000001.000001.000001.000001.000001.000001.000001.000000.07345011.000001.000001.291651.000000.7062650.3734151.189620.1906421.000001.00000

stderr

strace