verilog, 77 bytes

Result

WA

Code [DL]

module c;reg d;initial while($fscanf(1<<31,"%b",d))$write($sqrt(d));endmodule

stdin

01111001
10101011
00100100
00001111
01100111
00000100
01001110
10110100
11100111
11010111
01011011
11010010
00101111
11011110
00001010
00011100
11000100
00100000
10010010
00001010
10001001
00101000
01101001
01100000
00101101
10011001
01000010
00010101
00000000
01111000
10001000
10010101
00000011
11111111
11000101
01110010
10001100
11010011
00111000
00000110
00000001
00011001
10110010
11010000
00001000
11111101
00110111
01111010
00000011
10111110

stdout

1.000001.000000.000001.000001.000000.000000.000000.000001.000001.000001.000000.000001.000000.000000.000000.000000.000000.000000.000000.000001.000000.000001.000000.000001.000001.000000.000001.000000.000000.000000.000001.000001.000001.000001.000000.000000.000001.000000.000000.000001.000001.000000.000000.000000.000001.000001.000000.000001.000000.00000

stderr

strace