verilog, 83 bytes

Result

WA

Code [DL]

module c;integer d;initial while($fscanf(1<<31,"%b",d))$write($sqrt(d)%1);endmodule

stdin

00111111
00001010
01111000
00001111
01000110
00100100
00000110
10000010
01110001
01000010
11100111
00011100
01001110
10011111
00001100
00000001
10000111
11001111
00101101
10100010
01110010
10101011
11110000
01001010
11110011
00000100
11001100
10001011
01111000
10111111
01101010
10111110
10011001
00010101
11111101
00000000
11011101
10011001
00010010
10100000
01011011
01101001
10001000
00100111
10100100
11010010
00110111
00000011
01110100
11010001

stdout

0.9372540.1622780.9544510.8729830.3666000.000000.4494900.4017540.6301460.1240380.1986840.2915030.8317610.6095200.4641020.000000.6189500.3874950.7082040.7279220.6770780.07669680.4919330.6023250.5884570.000000.2828570.7898260.9544510.8202750.2956300.7840490.3693170.5825760.9059740.000000.8660690.3693170.2426410.6491110.5393920.2469510.6619040.2449980.8062480.4913770.4161980.7320510.7703300.456832

stderr

strace