verilog, 81 bytes

Result

WA

Code [DL]

module c;integer d;initial while($fscanf(1<<31,"%b",d))$write($sqrt(d));endmodule

stdin

00011100
01011001
11011010
00001010
11010010
01010100
11110101
00110111
00100001
00000110
00000001
01100111
10110100
00000111
00000000
11100111
10101100
00100100
00011101
11101101
10100001
10101011
10111110
00000011
10001000
00001111
00011111
01110101
00011001
01101001
10001011
10000100
01001110
00111110
01011111
00100111
10001000
10011001
11111101
00101101
00001111
00010101
01111000
01011011
01000010
10100011
10011000
10100110
01101100
01110001

stdout

5.291509.4339814.76483.1622814.49149.1651515.65257.416205.744562.449491.0000010.148913.41642.645750.0000015.198713.11496.000005.3851615.394812.688613.076713.78401.7320511.66193.872985.5677610.81675.0000010.247011.789811.48918.831767.874019.746796.2450011.661912.369315.90606.708203.872984.5825810.95459.539398.1240412.767112.328812.884110.392310.6301

stderr

strace