verilog, 77 bytes

Result

WA

Code [DL]

module c;reg d;initial while($fscanf(1<<31,"%b",d))$write($sqrt(d));endmodule

stdin

00000011
00001010
00010101
11000100
01111100
11010110
11111100
01001110
00000110
10111110
01100111
01010100
01111000
00100111
10101011
01011011
11011101
01000111
00100100
11100110
01101001
00110111
11111101
10100111
11111001
00000001
11101010
01000010
11111101
01001100
10001111
11010010
00000000
10001000
11001100
10101001
10000100
00001111
00010011
01111010
01011000
10011001
00101101
00101010
00011100
10101100
11010011
01011011
11101111
11100111

stdout

1.000000.000001.000000.000000.000000.000000.000000.000000.000000.000001.000000.000000.000001.000001.000001.000001.000001.000000.000000.000001.000001.000001.000001.000001.000001.000000.000000.000001.000000.000001.000000.000000.000000.000000.000001.000000.000001.000001.000000.000000.000001.000001.000000.000000.000000.000001.000001.000001.000001.00000

stderr

strace