verilog, 100 bytes

Result

WA

Code [DL]

module a;real x,y;initial repeat(50)begin scanf("%b",x);$write("%d",(8*x+1)**0.5%2==1);end endmodule

stdin

01000001
10001000
01101010
01000010
11111101
00000011
10001000
00001001
00011100
10011000
00110111
10011001
10111110
00001000
00111000
11010010
00001100
00100100
11001001
00000110
10001010
00001111
11100111
01100011
10101111
11110111
11011011
10010101
01010000
01001001
00001111
00111011
10001001
01000101
01011011
10101011
00101101
01000000
01101001
00000001
10100000
00111101
10011101
01111000
11101001
01001110
00010101
00001010
10100101
00000000

stdout

stderr

/volume/CODE:1: error: Enable of unknown task ``scanf''.
1 error(s) during elaboration.
/home/esolang/bin/verilog: line 4: /tmp/code: No such file or directory
rm: cannot remove '/tmp/code': No such file or directory

strace