verilog, 113 bytes

Result

WA

Code [DL]

module a;real x,y;initial repeat(50)begin
$fscanf(1<<31,"%b",x)
y=x**0.5
$write("%d",(y*8+1)%2==1)
end endmodule

stdin

11010011
00110111
11100111
11100000
11010010
10001000
00000011
00101011
01000010
00000001
01011100
00101101
10011001
01111000
11010111
00010110
10011001
01101001
01100101
00010101
10011100
10110010
00111100
01001110
10111110
01000100
00110100
01011011
11101000
11111101
00011100
00001001
11001101
10101011
10111001
01010010
01000011
10101010
00000000
01100000
01010011
00101010
00100100
00001010
01100010
00001111
00000110
10101111
10011000
10001000

stdout

stderr

/volume/CODE:3: syntax error
/volume/CODE:4: syntax error
/home/esolang/bin/verilog: line 4: /tmp/code: No such file or directory
rm: cannot remove '/tmp/code': No such file or directory

strace