verilog, 105 bytes

Result

WA

Code [DL]

module a;real x;initial repeat(50)begin fscanf(1<<31,"%b",x)
$write("%d",(8*x**0.5+1)%2==1);end endmodule

stdin

11100111
00110010
00011001
11111101
00010010
01011011
01001110
00000111
00010101
11010010
11111001
01001111
11110111
00011100
00000011
01111000
10011000
10101101
11010011
00001010
10101111
00110111
00100100
00000011
11110101
10111011
01010101
01101100
10101011
10101110
10110010
01011100
00101101
00001111
10010110
10001000
10011001
00111000
10111110
00100000
01101001
10011001
00000001
11101001
11010100
01000010
00000000
01000110
00000110
11101011

stdout

stderr

/volume/CODE:2: syntax error
/volume/CODE:2: error: malformed statement
/home/esolang/bin/verilog: line 4: /tmp/code: No such file or directory
rm: cannot remove '/tmp/code': No such file or directory

strace