by@progrunner17
WA
module c;wire c,d;initial begin while($fscanf(1<<31,"%b",d))begin for(c=1;d>0;c=c+1)d=d-c;$write(~|d);end end endmodule
10111110 00011100 00000011 00011110 11100111 00110111 10101001 00000001 01000111 11111101 10101011 00000010 00001110 00001100 00100100 01001110 01011011 01100100 01110101 11110101 00101101 11000010 01000001 01101011 01000010 00100110 10110001 01111000 00010101 11111110 00000110 10011001 01110110 10101101 10010101 00001010 01101001 00010111 11111101 00001111 01011000 10011011 00000111 00000000 10001000 11010010 11010111 10010010 11011001 01001110
/volume/CODE:1: error: d is not a valid l-value in c. /volume/CODE:1: : d is declared here as wire. 1 error(s) during elaboration. /home/esolang/bin/verilog: line 4: /tmp/code: No such file or directory rm: cannot remove '/tmp/code': No such file or directory