verilog, 85 bytes

Result

WA

Code [DL]

module c;
int i,j;
initial begin
j = fscanf(1<<31,"%b\n",i);
$write(i);
end
endmodule

stdin

00001011
01001110
00001111
00000001
00100100
10101011
01110010
01011011
00010101
00110111
00000011
00001010
10101001
00100010
10110110
11111000
00000000
01000000
01101001
10111101
00111001
10110111
10010001
11101001
00000110
10101010
10011001
11111101
11110100
10110101
11110111
10101101
01000010
11100111
00001111
11010010
01001111
10001111
10010101
00101101
00011100
00110010
11000101
01011000
10001000
01111000
11000000
11011100
00011100
10111110

stdout

stderr

/volume/CODE:2: syntax error
/volume/CODE:2: error: Invalid module instantiation
/home/esolang/bin/verilog: line 4: /tmp/code: No such file or directory
rm: cannot remove '/tmp/code': No such file or directory

strace