verilog, 139 bytes

Result

WA

Code [DL]

module a;integer i,j,x,c;initial repeat(50)begin $fscanf(1<<31,"%b",x);for(c=j=0;j<=x;j=j+1)c=c+(j*(j+1)/2==x);$write("%d",c);end endmodule

stdin

00000001
01000010
10001101
01111000
10110010
00010101
10010110
10000011
00011000
00100100
11100111
11000101
10111111
11100111
10001000
01011011
01111010
00001011
00111111
01101001
11001111
00100100
10101011
00100110
10110110
00101101
11000000
01110100
00000110
00000000
10011001
11010010
00011100
00001010
11111001
11111101
10000010
01111011
00010111
00000011
00001111
00110111
10111110
01111110
01011110
01001110
00001000
00110100
01000100
01000001

stdout

stderr

/volume/CODE:1: syntax error
/volume/CODE:1: error: Incomprehensible for loop.
/home/esolang/bin/verilog: line 4: /tmp/code: No such file or directory
rm: cannot remove '/tmp/code': No such file or directory

strace