verilog, 160 bytes

Result

WA

Code [DL]

module a;integer i,j,x,c;initial begin for(;;)begin c=$fscanf(2147483648,"%b",x);for(j=50;--j>0;j)begin c=c+(j*(j+1)/2==x);end $writeb("",c-1);end end endmodule

stdin

01111000
11101101
00001010
01011011
00001000
00000000
01001101
00001111
01001010
00010101
00100111
10110111
01100001
01111011
11100111
10101011
10101001
11111101
10110100
00011010
00010000
10001000
11010010
00000110
11100111
00101101
11101010
00101010
01100111
11100110
01001110
10001100
00011100
10100100
10100001
01000010
00110111
01110011
11100101
00011100
00111100
00100100
00010011
00000001
01111101
10010111
00000011
10011001
10111110
01101001

stdout

stderr

/volume/CODE:1: syntax error
/volume/CODE:1: syntax error
I give up.
/home/esolang/bin/verilog: line 4: /tmp/code: No such file or directory
rm: cannot remove '/tmp/code': No such file or directory

strace