by@progrunner17
WA
module c;integer c,d;initial begin repeat(50)begin d=0;c=48;repeat(9)begin d=d*2+c-48;c=1<<31;c=$fgetc(s);end for(c=1;d>0;c=c+1)d=d-c;$write("%d",~|d);end end endmodule01010011 01101101 11110011 10011001 00001010 00000110 00100100 00101000 00110111 01110001 01100111 01000010 00010101 01000010 00000001 10111000 01110111 00101010 00011111 10010000 10000101 00000000 00101101 01110101 10101011 10011000 00000101 11100001 10001000 01110100 11101010 11101110 01101001 10011110 00000011 11001000 01001110 01111000 00011100 01011011 00001111 01101111 10111110 00110111 11111000 11001011 01111011 11010010 11100111 11111101
/volume/CODE:1: error: Unable to bind wire/reg/memory `s' in `c' ivl: netmisc.cc:467: void eval_expr(NetExpr*&, int): Assertion `expr' failed. Aborted (core dumped) /home/esolang/bin/verilog: line 4: /tmp/code: No such file or directory rm: cannot remove '/tmp/code': No such file or directory