verilog, 170 bytes

Result

WA

Code [DL]

module c;integer c,d;while(!(&c))begin d=0;c=48;while(c!=10)begin d=d*2+c-48;c=1<<31;c=$fgetc(c);end c=1;while(d>0)begin d=d-c;c=c+1;end $write("%d ",!(&d));end endmodule

stdin

00011100
00100100
00110111
11100111
10101000
11010101
10101100
10111110
00000011
00000000
01101001
10001111
10100011
10101111
00000110
01110010
00101101
00000000
10011110
01111000
10101011
01001110
00010101
01111011
10011001
11111001
10110000
01011001
01110111
01011100
00100011
10110101
01010010
01000010
00010100
11111101
11010010
11010111
00000001
10111100
00111011
10001000
01011111
01000011
00000011
11010000
00001010
10000101
01011011
00001111

stdout

stderr

/volume/CODE:1: syntax error
/volume/CODE:1: error: invalid module item.
/volume/CODE:1: syntax error
/volume/CODE:1: error: Invalid module instantiation
/volume/CODE:1: error: invalid module item.
/volume/CODE:1: syntax error
/volume/CODE:1: error: Invalid module instantiation
/volume/CODE:1: error: Invalid module instantiation
/volume/CODE:1: error: invalid module item.
/volume/CODE:1: syntax error
/volume/CODE:1: error: invalid module item.
/volume/CODE:1: syntax error
/volume/CODE:1: error: Invalid module instantiation
/volume/CODE:1: error: invalid module item.
/volume/CODE:1: syntax error
I give up.
/home/esolang/bin/verilog: line 4: /tmp/code: No such file or directory
rm: cannot remove '/tmp/code': No such file or directory

strace