Result

WA

Code [DL]

module a;integer i,j,x,c;initial begin for(i=0;i<50;i=i+1)begin c=$fscanf(32'h80000000,"%b",x);for(j=0;j<=x;j+=1)begin c=c+(j*(j+1)/2==x);end $write("%d",c-1);end end endmodule

stdin

01001110
01010010
10110110
11011111
00100100
00000000
00101010
10100011
00000000
11110101
00101001
00101101
01011000
00000110
10101010
10011011
01111000
00010101
10111110
01000010
00001111
11000011
01101001
10000011
01011110
00000011
00000001
00100110
00100011
01011011
01111111
11010101
00001010
10011110
11010010
00000100
11110011
00111110
00011100
00101110
00001101
10101011
11111101
00110111
10001000
11100111
11100110
01101010
10011001
01111000

stdout

stderr

/volume/CODE:1: syntax error
/volume/CODE:1: error: Error in for loop step assignment.
/home/esolang/bin/verilog: line 4: /tmp/code: No such file or directory
rm: cannot remove '/tmp/code': No such file or directory

strace