Result

AC

Code [DL]

module a;
	integer i,j,x,c;
	initial begin
		for (i=0;i<50;i=i+1) begin
			c = $fscanf(32'h8000_0000,"%b",x);
			for(j=0;j<=x;j=j+1) begin
				if (j*(j+1)/2==x) begin
					c = 0;
				end
			end
			$write("%d",1-c);
		end
	end
endmodule

stdin

10101010
11001010
11100111
00010001
11111001
10001000
00100100
11100110
01010010
00101101
11111101
00000110
00001110
10100111
00000001
00011100
01101001
10000011
00000000
01011011
00100011
00111001
00010010
00111100
10111110
11011011
11100001
11010100
01001110
00001111
00101110
00010101
00000011
00101100
01000001
00001111
11111000
01111000
11100010
01110100
10011001
00001010
11110011
00110111
01000010
00101011
01011110
10101011
11010010
11010010

stdout

          0          0          1          0          0          1          1          0          0          1          1          1          0          0          1          1          1          0          1          1          0          0          0          0          1          0          0          0          1          1          0          1          1          0          0          1          0          1          0          0          1          1          0          1          1          0          0          1          1          1

stderr

strace