verilog, 247 bytes

Result

WA

Code [DL]

module c;integer c,d,s;initial begin s=1<<31;c=$fgetc(s);while(|!c)begin d=0;while(c!=10)begin d=d*2;d=d+c-48;c=$fgetc(s);end c=1;while(d>0)begin d=d-c;c=c+1;end if(d)begin $write("0 ");end else begin $write("1 ");end c=$fgetc(s);end end endmodule

stdin

00011100
11010010
10011111
00000001
10101011
10001000
00001100
01011010
10000000
11110101
10111101
00000011
10010001
01101100
01101001
10111000
00111000
00001111
00001000
01011011
00001010
11010001
01000010
01111000
00010110
11111101
01001101
11111100
11000100
00100100
01001110
00110111
00010101
10110000
10111110
11000001
10011001
11100111
10011110
10110010
11100110
11001011
00101101
00000001
00101111
11010011
10111100
01111000
00000000
00000110

stdout

stderr

/volume/CODE:1: syntax error
/volume/CODE:1: error: Error in while loop condition.
/home/esolang/bin/verilog: line 4: /tmp/code: No such file or directory
rm: cannot remove '/tmp/code': No such file or directory

strace