by@satos___jp
WA
module a;
integer i,j,x,c;
initial begin
for (i=0;i<10;i=i+1) begin
c = $fscanf(32'h8000_0000,"%b",x);
for(j=0;j<x;j++) begin
if (j*(j+1)/2==i) begin
c = 0
end
end
$write("%d\n",1-c);
end
end
endmodule
10110000 11101101 01011000 00101101 11010010 01001110 01110000 10001000 11111101 11010010 10011001 00000110 00110111 00000101 00110111 10110010 11110111 11101111 11000000 10111110 01001000 00001111 01101001 10111011 00100110 00000001 10110110 00100100 00010101 10100100 01101110 01011011 01111000 00101001 01111101 10010100 00000011 00100101 00001000 00011000 10101011 11110101 00000000 01000010 11100111 00001010 01100100 00011100 10010110 01111100
/volume/CODE:6: syntax error /volume/CODE:9: syntax error /volume/CODE:6: error: Error in for loop step assignment. /home/esolang/bin/verilog: line 4: /tmp/code: No such file or directory rm: cannot remove '/tmp/code': No such file or directory