verilog, 205 bytes

Result

WA

Code [DL]

module cat;
	integer c,i,j,x,y;
	initial begin
		for (i=0; i<10; i++) begin
			x = 0;
			for (j=0;j<8;j++) begin
				x = x * 2 + $fgetc(32'h8000_0000) - 48;
			end
			$write("%d", x);
		end
	end
endmodule

stdin

01000100
00001010
00110001
00011011
11100111
00000000
01101001
00000110
10111000
11111101
01011000
00101101
00111011
00001111
01011011
10011000
10011001
00001101
10101111
00010001
01111000
00000100
01001110
00100100
10001000
01101011
10111101
10001110
11101100
10101011
11111100
00011110
11000001
00010101
11010010
10111110
11111001
00000001
11010001
11100111
00001110
00000011
00110111
01010010
11010011
10001000
00011100
01000010
11100110
00010000

stdout

stderr

/volume/CODE:4: syntax error
/volume/CODE:6: syntax error
/volume/CODE:6: error: Error in for loop step assignment.
/volume/CODE:4: error: Error in for loop step assignment.
/home/esolang/bin/verilog: line 4: /tmp/code: No such file or directory
rm: cannot remove '/tmp/code': No such file or directory

strace