verilog, 205 bytes

Result

WA

Code [DL]

module cat;
	integer c,i,j,x,y;
	initial begin
		for (i=0; i<10; i++) begin
			x = 0
			for (j=0;j<8;j++) begin
				x = x * 2 + $fgetc(32'h8000_0000) - 48;
			end
			$write("%d", x);
		end
	end
endmodule

stdin

01101001
10000110
01111000
11111101
00110111
10111011
00101111
11010001
10011001
00000011
11100011
00000001
01011011
10100110
11111110
00001010
01100110
01011100
11010010
00000000
10111110
01001101
00100100
00110001
01000010
01100100
11000111
01111010
11010101
00011111
00001111
00101101
00000110
10010111
11100111
00011001
10100100
00000000
01001110
10001000
00011100
00010101
01011001
00001010
11001101
00111110
00010100
00100101
10101011
11100000

stdout

stderr

/volume/CODE:5: syntax error
/volume/CODE:7: syntax error
/volume/CODE:7: Syntax in assignment statement l-value.
/volume/CODE:7: syntax error
/volume/CODE:7: error: malformed statement
/volume/CODE:7: syntax error
/volume/CODE:8: Syntax in assignment statement l-value.
/volume/CODE:5: error: Error in for loop step assignment.
/volume/CODE:12: syntax error
I give up.
/home/esolang/bin/verilog: line 4: /tmp/code: No such file or directory
rm: cannot remove '/tmp/code': No such file or directory

strace