verilog, 270 bytes

Result

WA

Code [DL]

module cat;int c,i,d,s;initial begin s=1<<32; c=$fgetc(s);while(!(&c))begin d=0;i=1;while(c==48||c==49)begin d=d*2;d=d+c-48;c=$fgetc(s);end i=1;while(d>0)begin d=d-i;i=i+1;end if(d==0)begin $write("%d ",1);end else begin $write("%d ",0);end c=$fgetc(s);end end endmodule

stdin

00010101
00000111
00001010
01101001
00011100
01010111
01011101
01110011
11011011
00100100
11111101
01101011
11110001
10001011
01001110
01101111
11000111
00110111
11100111
01011011
01000010
00001111
10111110
01100011
01011011
00010011
11011000
10001000
00000001
00000110
00101101
10011010
10101011
10000010
10000100
01111000
00011000
01011100
00010110
01011001
00000000
01101001
11110111
11001001
10111101
10011001
10000001
11010010
00000011
10100011

stdout

stderr

/volume/CODE:1: syntax error
/volume/CODE:1: error: Invalid module instantiation
/home/esolang/bin/verilog: line 4: /tmp/code: No such file or directory
rm: cannot remove '/tmp/code': No such file or directory

strace