verilog, 270 bytes

Result

WA

Code [DL]

module cat;int c,i,d,s;initial begin s=1<<32; c=$fgetc(s);while(!(&c))begin d=0;i=1;while(c==48||c==49)begin d=d*2;d=d+c-48;c=$fgetc(s);end i=1;while(d>0)begin d=d-i;i=i+1;end if(d==0)begin $write("%d ",1);end else begin $write("%d ",0);end c=$fgetc(s);end end endmodule

stdin

00010101
00011100
01101001
10100011
01001110
10001000
00101111
11111101
00100100
01010101
00000000
10000001
11110001
10110101
10011010
10111110
00010010
10101011
10011001
00001111
10100111
10010101
11001000
00101101
00000001
01001100
00001010
01000010
01011000
11010010
10101000
00000110
00000110
00100010
00011110
01111000
00011011
00110111
00001000
11100111
10010011
00101100
01000000
10111110
11010101
01011011
00111000
10100010
00000011
01100001

stdout

stderr

/volume/CODE:1: syntax error
/volume/CODE:1: error: Invalid module instantiation
/home/esolang/bin/verilog: line 4: /tmp/code: No such file or directory
rm: cannot remove '/tmp/code': No such file or directory

strace