verilog, 525 bytes

Result

WA

Code [DL]

`define EOF 32'hFFFF_FFFF
`define STDIN 32'h8000_0000

module cat;
	integer c,i,d;
	initial begin
	c = 48;
		while (c != `EOF) begin
			c = $fgetc(`STDIN);
			d = 0;
			i = 1;
			while ( c == 48 || c == 49)begin
				d = d + (c - 48) * i;
				i =  i * 2;
				c = $fgetc(`STDIN);
			end
			d = d/4;
		    $write("%d\n", d);
			i = 1;

			while(d > 0)begin 
				d = d - i;
				i = i + 1;
			end

			if ( d == 0 )begin
				// $write("%c\n", "0");
		    end else begin
		    	// $write("%c\n", "1");
		    end
		end
	end
endmodule

stdin

00000001
01111001
11111110
01100010
01001001
00001111
00011100
01000010
11011000
00011011
10101011
00110111
11010111
00001111
10011001
01101001
00100001
11010010
01101011
10111110
11111101
00000110
00000111
01100000
00101110
11110011
01011011
01110010
11110010
11111111
00001010
01111101
01111000
01100001
10001000
01001110
11011111
00011110
00101101
10110000
11100111
00000000
00010101
00100000
00100100
11000010
01000010
00000011
10001110
00111010

stdout

         32
         39
         31
         17
         36
         60
         14
         16
          6
         54
         53
         59
         58
         60
         38
         37
         33
         18
         53
         31
         47
         24
         56
          1
         29
         51
         54
         19
         19
         63
         20
         47
          7
         33
          4
         28
         62
         30
         45
          3
         57
          0
         42
          1
          9
         16
         16
         48
         28
         23
          0

stderr

strace