verilog, 273 bytes

Result

WA

Code [DL]

`define S 32'h80000000
module q;
integer c,x;
initial begin
	for(l=0;l<50;l=l+1)begin
		for(i=0;i<8;i=i+1)begin
			c=$fgetc(`S)&1;
			x=x+c;
			x=x<<1;
		end
		c=$fgetc(`S)
		for(i=0;;i=i+1)begin:A
			if(x>0)disable A;
			x=x-i;
		end
		$write("%d",x==0?1:0)
	end
endmodule

stdin

01010101
00010101
10111111
10111001
10010001
00001111
10101001
00000011
01011011
11000111
10101011
00100100
00000010
10001000
10101111
10100011
10011001
00110100
00000001
11101110
11001010
01111101
11000001
00011100
01111001
01001110
01000010
00101101
11111001
10000101
01101001
00000110
00000000
00101010
01111000
10011110
01101010
00001111
11111101
11010010
00001010
11000011
11100111
11010001
00110111
11111101
10111110
11101010
01011110
00100000

stdout

stderr

/volume/CODE:12: syntax error
/volume/CODE:12: Syntax in assignment statement l-value.
/volume/CODE:12: syntax error
/volume/CODE:12: error: malformed statement
/volume/CODE:12: syntax error
/volume/CODE:13: error: malformed statement
/volume/CODE:17: syntax error
I give up.
/home/esolang/bin/verilog: line 4: /tmp/code: No such file or directory
rm: cannot remove '/tmp/code': No such file or directory

strace