verilog, 321 bytes

Result

WA

Code [DL]

`define EOF 32'hFFFF_FFFF
`define STDIN 32'h8000_0000

module cat;
	integer c,i,d;
	initial begin
		c = $fgetc(`STDIN);
		i = 1;
		d = 0;
		while (c != `EOF) begin
			while ( c != 10)begin
				d = (c - 48) * i;
				i =  i * 2;
				c = $fgetc(`STDIN);
			end
			$write("%d", d);
			c = $fgetc(`STDIN);
		end
	end
endmodule

stdin

11111101
01000001
00000110
00011100
11000101
00001111
10100010
10111111
01111000
01101001
10011001
00010001
01000010
00111110
00101101
00110001
00101110
00001010
00100101
11100111
01010100
01000010
00011101
11101100
00000011
10101001
10110100
01010001
10001000
10101011
10111110
00110111
00100100
11001100
00000000
01011110
11010010
11011001
11110110
00001111
00010010
01001110
10001010
00000001
01010111
01011011
10010111
00010101
01010000
10010101

stdout

        128      32768          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0

stderr

strace