verilog, 282 bytes

Result

WA

Code [DL]

`define EOF 32'hFFFF_FFFF
`define STDIN 32'h8000_0000

module cat;
	integer c,i,d;
	initial begin
		c = $fgetc(`STDIN);
		i = 1;
		d = 0;
		while (c != `EOF) begin
			while ( c != 10)begin
			c = $fgetc(`STDIN);
			end
			$write("%d", c);
			c = $fgetc(`STDIN);
		end
	end
endmodule

stdin

00000000
01010010
10011001
11100111
11100011
10010010
00010101
11010010
00010000
00001001
00101101
10111100
01000010
11011111
00000110
10100000
01100011
00001010
00100100
00111011
01001010
00001011
01101001
01011011
10111110
01000111
01001100
00100111
00011110
10110011
01111000
10101011
10001111
11111101
01001111
10011111
00011100
00000011
10010100
10001000
10101101
00000001
11010010
01001110
01111100
11111101
11011001
00110111
00001111
11000011

stdout

         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10         10

stderr

strace