verilog, 237 bytes

Result

WA

Code [DL]

`define S 32'h80000000
module q;
integer c,x;
initial begin
	for(l=0;l<50;l=l+1)begin
		for(i=0;i<8;i=i+1)begin
			c=$fgetc(`S)&1;
			x=x+c;
			x=x<<1;
		end
		c=$fgetc(`S)
		for(i=0;x>0;i=i+1)x=x-i;
		$write("%d",x==0?1:0)
end
endmodule

stdin

01100111
01100010
00000000
00111100
10111000
10001001
00010101
11100110
00011100
10101101
11100101
00001111
11001100
10111110
10100110
01011011
11110000
11100111
01101101
10100011
10101011
01101110
00110111
10011000
00110111
01000010
00000010
00100100
00000110
10001000
10000111
11000111
00101101
10001110
00110101
00000011
11010010
01000011
10001011
01111000
11111101
01101001
00001010
00000001
01111110
10011001
11101011
10001000
01000111
01001110

stdout

stderr

/volume/CODE:12: syntax error
/volume/CODE:12: Syntax in assignment statement l-value.
/volume/CODE:12: syntax error
/volume/CODE:12: error: malformed statement
/volume/CODE:12: syntax error
/volume/CODE:12: Syntax in assignment statement l-value.
/volume/CODE:14: syntax error
I give up.
/home/esolang/bin/verilog: line 4: /tmp/code: No such file or directory
rm: cannot remove '/tmp/code': No such file or directory

strace