verilog, 207 bytes

Result

WA

Code [DL]

`define EOF 32'hFFFF_FFFF
`define STDIN 32'h8000_0000

module cat;
	integer c,i;
	initial begin
		c = $fgetc(`STDIN);
		while (c != `EOF) begin
			$write("%c", d);
			c = $fgetc(`STDIN);
		end
	end
endmodule

stdin

01110011
00000001
00110111
01100011
01001010
11100111
00010111
10111110
11001010
11000110
01001110
00001111
01111100
00010101
11010011
00011100
00011011
00101101
01111000
11111101
00000110
01111111
00000110
00010100
11101000
00100000
00100100
10101011
11110100
10011110
11000010
00100011
01001110
01101001
00111010
01011011
01000010
10001000
01100101
00001100
00100110
00000011
10100110
10011001
01010101
01110111
11010010
00000000
00010001
00001010

stdout

stderr

/volume/CODE:9: error: Unable to bind wire/reg/memory `d' in `cat'
1 error(s) during elaboration.
/home/esolang/bin/verilog: line 4: /tmp/code: No such file or directory
rm: cannot remove '/tmp/code': No such file or directory

strace