verilog, 233 bytes

Result

WA

Code [DL]

`define S 32'h80000000
module q;
integer c,x;
initial begin
	for(l=0;l<50;l=l+1)begin
		for(i=0;i<8;i=i+1)begin
			c=$fgetc(`S)&1;
			x=x+c;
			x=x<<1;
		$fgetc(`S)
		for(i=0;x>0;i=i+1)x=x-i;
		$write("%d",x==0?1:0)
end
end
endmodule

stdin

01001010
00001010
01010011
11010010
01001101
01101001
00110100
10001000
00101001
01111000
00100100
00110001
01000001
00101100
00101101
00000001
00000111
10001011
10111110
01111010
10011001
01000010
00011100
11110010
00011100
00001100
00101010
10101011
11100111
11100010
11011000
10101000
01011011
01001110
01101001
10010010
00111011
10000001
00111100
00010101
00000110
00000011
00110111
11111101
00001111
01011101
00000000
01000110
11010011
10110010

stdout

stderr

/volume/CODE:11: syntax error
/volume/CODE:11: Syntax in assignment statement l-value.
/volume/CODE:11: syntax error
/volume/CODE:11: error: malformed statement
/volume/CODE:11: syntax error
/volume/CODE:11: Syntax in assignment statement l-value.
/volume/CODE:13: syntax error
I give up.
/home/esolang/bin/verilog: line 4: /tmp/code: No such file or directory
rm: cannot remove '/tmp/code': No such file or directory

strace