verilog, 214 bytes

Result

WA

Code [DL]

`define S 32'h80000000
module q;
integer c,x;
initial begin
	for(l=0;l<50;l=l+1)begin
		for(i=0;i<8;i=i+1)begin
			c=$fgetc(`S)[0];
			x=x+c;
			x<<1;
		$fgetc(`S)
		for(i=0;x>0;i=i+1)x=x-i;
		$write("%d",x==0?1:0)

stdin

01101001
01000101
11110110
11100101
00000110
10001000
01101010
11111101
11100110
00100000
01110010
11000101
00000001
10111110
00011100
00110111
10101011
11111111
11000100
01111001
00001010
00000110
01001110
01000001
00000011
00000000
00111110
01111000
10110011
10010000
11001000
00100101
11100111
11010111
11011100
00010101
10011001
10101111
00100100
00101101
01000010
10100011
11010000
00001111
11010010
00000000
10111000
01011011
11111000
00001101

stdout

stderr

/volume/CODE:7: syntax error
/volume/CODE:7: error: malformed statement
/volume/CODE:9: syntax error
/volume/CODE:9: error: malformed statement
/volume/CODE:11: syntax error
/volume/CODE:11: Syntax in assignment statement l-value.
/volume/CODE:11: syntax error
/volume/CODE:11: error: malformed statement
/volume/CODE:11: syntax error
/volume/CODE:11: Syntax in assignment statement l-value.
/volume/CODE:12: syntax error
I give up.
/home/esolang/bin/verilog: line 4: /tmp/code: No such file or directory
rm: cannot remove '/tmp/code': No such file or directory

strace